AMD HIP-RT 3.2.0更新新增三款Medusa APU iGPU,混合RDNA 4m与RDNA 3.5
AMD’s HIP-RT 3.2.0 Update Adds Three New Medusa APU iGPUs, Mixing RDNA 4m With RDNA 3.5
AMD发布HIP-RT 3.2.0更新,新增三款Medusa APU iGPU(GFX1171、GFX1170、GFX115E)支持,它们混合RDNA 4m与RDNA 3.5架构。该库更新还包含性能改进与修复,Medusa APU家族将分层搭载不同RDNA架构iGPU以应对Intel Xe3竞争。
AMD Medusa APUs and their iGPUs, which will be a mix of RDNA 4m & RDNA 3.5 generations, have received support in the HIPRT library.
AMD's Future iGPU Trio Gets Added To HIP-RT Library As Medusa APU Support Keeps Cooking
AMD has recently released the latest update to its HIP Ray Tracing library in the form of v3.2.0. This new version comes with many changes, new features, performance improvements, and a range of bug fixes. But one of the most significant updates is that it adds support for next-gen Medusa APUs.
The HIP-RT library support for Medusa APUs comes in the form of three new iGPU IDs, which include GFX1171, GFX1170, and GFX115E. There isn't a whole lot of detail available on these iGPUs within the release, but from earlier leaks, we know that the GFX117X series is based on AMD's RDNA 4m architecture while the GFX115X is based on the RDNA 3.5 IP.

Earlier leaks have pointed to RDNA 4m being a mix of RDNA 3.5 and RDNA 4.0 architectures. At least one other GPU ID was confirmed earlier in addition to GFX1170 and GFX1171, & that is the GFX1172.
The GFX115E ID is part of the RDNA 3.5 family and could be an "Enhanced" or "Efficiency" variant. We know that AMD will be using a mix of iGPUs across its Medusa Point APU family. RDNA 3.5 is going to power the entry-level and mainstream designs, while other models will feature the new RDNA 4M IP.
Previous reports suggest that AMD will also offer RDNA 5 iGPUs across its Medusa lineup but only on premium SoCs, likely the Halo models. Medusa Premium is expected to feature an RDNA 5 "AT4 GMD" die, while Medusa Halo is expected to feature an RDNA 5 "AT3 GMD" die. These dies will be separate from the main compute tiles, and the monolithic version will be Medusa Point, which will retain RDNA 3.5 iGPUs.

For Medusa, AMD is expected to increase the core counts and add some optimizations in a specific class of APUs to make the iGPU part competitive against Intel's lineup, which just got upgraded to Xe3, promising a big bump in performance and far exceeding the capabilities of AMD's mainstream APU family. Also this year, Intel is expected to roll out Xe3P, a brand new architecture leveraging the Celestial design, under a brand new Arc D-Series family.
AMD Ryzen APU "iGPU" Configurations:
| APU Family | Codename | GPU Codename | GPU Compute Units (Max) | TFLOPs |
|---|---|---|---|---|
| Ryzen 2000 | Raven Ridge | Vega | 11 Compute Units | 1.76 TFLOPs |
| Ryzen 3000 | Picasso | Vega | 11 Compute Units | 1.97 TFLOPs |
| Ryzen 4000 | Renoir | Vega+ | 8 Compute Units | 2.15 TFLOPs |
| Ryzen 5000 | Cezanne | Vega+ | 8 Compute Units | 2.04 TFLOPs |
| Ryzen 6000 | Rembrandt | RDNA 2 | 12 Compute Units | 3.40 TFLOPs |
| Ryzen 7000 | Phoenix Point | RDNA 3 | 12 Compute Units | 8.30 TFLOPs |
| Ryzen AI 300 | Strix Point | RDNA 3.5 | 16 Compute Units | 5.93 TFLOPs |
| Ryzen AI MAX 300 | Strix Halo | RDNA 3.5 | 40 Compute Units | 14.85 TFLOPs |
| Ryzen AI 400 | Gorgon Point | RDNA 3.5 | 16 Compute Units | ~8.50 TFLOPs |
| Ryzen AI MAX 400 | Gorgon Halo | RDNA 3.5 | 40 Compute Units | ~15.00 TFLOPs |
| Ryzen AI 500 | Medusa Point | RDNA 3.5+ | TBD | TBD |
| Ryzen AI 500 | Medusa Premium | RDNA 5 | TBD | TBD |
| Ryzen AI MAX 500 | Medusa Halo | RDNA 5 | TBD | TBD |
| Ryzen AI 600 | TBD Point | RDNA 5 | TBD | TBD |
| Ryzen AI MAX 600 | TBD Halo | RDNA 5 | TBD | TBD |
News Source: Phoronix
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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来源:Wccftech · wccftech.com